Voltage translators are typically employed to convert logic level drive control signals into output signals suitable for driving a load. Often, the output drive signal exceeds the voltage level of the logical control signal. In this case, the voltage translator acts as a voltage amplifier or isolator. A voltage translator for digital logical control signals should have low average and peak power dissipation, small cell size, fast load switching, and possibly with controlled output slew rate (to avoid generation of electromagnetic interference and switching transients).
A typical voltage translator circuit provides a four transistor cell having two pull down NMOS transistors, referenced to a common ground, which are complementarily driven by a logic control signal and an inverter, respectively, and two pull up PMOS transistors, referenced to a medium voltage, typically higher than the logic power supply reference voltage, which are "cross coupled" to provide positive feedback. A complementary output is produced at the respective nodes between the PMOS and NMOS transistors.
In alternate known designs, the PMOS transistor is replaced with a resistive structure, providing a continuous quiescent current draw during the full pulse period. Alternately, for heavy loads, the high and low side logic may be separately controlled. Such designs, however, are typically unsuitable for modern high density integrated circuits which contain many voltage translators which switch essentially in synchronism.
One of the known advantages of reflective active matrix projection display devices with liquid crystal on silicon is that the drivers can be integrated with the active matrix itself. This allows improved performance and reliability, with lowered total system cost.
In one type of design, an analog reference ramp digital-to-analog converter (D/A) scheme is used to convert digital logic-level incoming data signals 1 into analog column voltages on the panel. A global analog ramp 3 signal is generated every row period 7. Each column tracks the global analog ramp signal, until it reaches its intended gray scale. At that time, it is controlled to stop tracking, and holds its voltage till the end of the row period. The digital data for each respective individual column are converted into simultaneous, pulse width modulated signals. The pulse width modulated signals control the analog track-and-hold switches 4 between respective columns and the global analog ramp 3 signal. In this way the digital video data are converted into analog voltages on the columns. This arrangement is shown in FIG. 1.
As shown in FIG. 1, column data 1 is received by logic circuit 2, to control the modulation of the liquid crystal display (LCD) pixels 8. A global analog ramp 3 is generated in each row period 7, which is selectively latched by track and hold switches 4, based on an individual pulse width timing generated by the logic circuit 2. The latched analog ramp voltage on each column 5 is used to drive the corresponding liquid crystal display pixel of the selected row. At the end of each row period 7, an end of row select signal 6 resets the track and hold switches 4, preparing for driving the next row.
FIG. 2 shows a prior art voltage translator circuit system. A tracking signal 10 is received for each column, from the logic circuit 2. A buffer 16 and inverter 17 (or pair of inverters) buffer the signal and generate a complementary pair, for driving the voltage translator 12 itself. The voltage translator converts the standard logic 11 voltage levels to a medium voltage level, generated by the medium voltage power supply 14. The voltage translator 12 has two complementary branches, each having an NMOS transistor 18, 19, for active pull down, and a PMOS transistor 20, 21, for active pull up, in series. Each PMOS transistor 20, 21 is driven with positive feedback from the node between the NMOS and PMOS transistor of the complementary branch. These same nodes are used here to drive an analog transmission gate 13 including an NMOS transistor 22 and PMOS transistor 23, to control the track and hold of the global analog ramp signal 15, which drives each column. The logic to generate the pulse width modulated signals for each column is standard low voltage, e.g. 5V or less, but each track & hold switch has to handle the analog voltage range for the columns, which is generally larger than the standard logic voltage swing, e.g., 5V peak or more power supply voltage, typically 12 V min. A voltage translator circuit is provided for each column to convert the logical control signal into the potentially higher voltage drive signal. The voltage translator circuit therefore translates a complementary signal pair at standard logic voltages into a medium voltage signal pair. A known voltage translator circuit is shown in FIG. 2. Such a voltage translator circuit is disclosed in U.S. Pat. No. 5,723,986 and U.S. Pat. No. 5,682,174, expressly incorporated herein by reference, and JP 07-168,153 (Apr, 7, 1995). See, also U.S. Pat. No. 5,473,268, expressly incorporated herein by reference.
The track and hold switch is shown as a transmission gate 13 in FIG. 2, but other implementations are also possible. The known voltage translator 12 shown in FIG. 2 uses internal positive feedback to switch. Whenever the complementary inputs switch, one branch is temporarily floating (both the bottom NMOS transistor and the top PMOS transistor are "Off"), while the other branch draws heavy current (both NMOS and PMOS transistor are "On"). When the active NMOS transistor pulls the gate of the passive PMOS over the threshold voltage, it starts conducting and positive feedback occurs to complete the switch event. The gate of each NMOS transistor (18,19) is driven with logic voltage levels, and yet has to compete with the PMOS transistor that has essentially the full medium voltage power supply 14 voltage swing on its gate. Therefore, the NMOS transistors have to be substantially larger than the PMOS transistors (20,21), in order to pull the junction node voltage to a low enough level to turn the PMOS transistor in the other branch "On".